Two years after IBM created the world’s first 7 nanometer chip, the company said it has now developed a breakthrough process to build an even more densely-packed chip at 5nm.
The chip will pack 30 billion 5nm switches onto a chip the size of a fingernail. For context, IBM’s 7nm test chip packed 20 billion transistors on a chip of the same size.
Essentially, the more densely transistors are packed onto a chip, the faster the signals can pass between the transistors. With the increased transistor density, IBM said the 5nm chip achieves 40% performance boost, or 75% power efficiency with the same performance, over the current-generation 10nm chips coming out now.
IBM’s said it’s using a new type of transistor, called stacked silicon nanosheets, to pack transistors this closely together. The nanosheet transistor sends electrons through four gates, as opposed to the current-generation FinFET transistor design that sends electrons through three gates. FinFET (short for fin field-effect transistor) began appearing in 22nm and 14nm chips and are expected to continue being used with 7nm chips.
The chip industry is racing to move beyond the FinFET design because it doesn’t scale anymore, said Mukesh Khare, vice president of semiconductor technology research at IBM Research. As chip designers cram more transistors closer together, chips are confronting issues with transistor leakage.
“Geometrically, FinFETs cannot scale anymore,” Khare said.
IBM has been researching this nanosheet transistor chip technology for over a decade now. The company uses Extreme Ultraviolet lithography to manufacture the nanosheet transistor design — the same process applied to IBM’s 7nm test chip.
The 5nm chip research is coming out IBM’s Research Alliance with chip foundry partners GlobalFoundries and Samsung. The Alliance announced the chip at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. IBM doesn’t manufacture chips anymore, but GlobalFoundries and Samsung do and they have the option to license the 5nm process.
5nm chips are expected to start manufacturing at scale around the 2020 timeframe.
The current-generation chips actually out in products are at the 10nm process node. For example, Qualcomm’s latest mobile processor, the Snapdragon 835, is one of the first chips using Samsung’s 10nm fabs and are currently found in the Samsung’s latest Galaxy S8 smartphone.
As IBM comes out with the 5nm chip design, the chip industry is facing huge difficulties keeping up with pace of Moore’s Law, the economic law named after Intel cofounder Gordon Moore that predicts the number of transistors packed onto the same size of silicon will double around every two years. IBM’s 5nm design gives the industry a direction to move towards until at least 2020.
“Moore’s Law is constantly being challenged because it’s not easy,” Khare said. “It constantly requires fundamental breakthroughs. The new transistors will enable [the chip industry] to continue scaling and generate the economic value Moore’s Law has predicted.”
Nevertheless, with the chip industry still facing uncertainties around whether the pace of Moore’s Law can endure, some chip designers are exploring alternatives. Instead of cramming more transistors onto a chip, some of the leading developments in chips these days are coming from new designs in processor architecture. Graphics processing units, for example, have become a dominant method of accelerating training for a form of artificial intelligence called deep learning. And Google has begun developing their own dedicated chips, called Tensor Processing Units, targeted at boosting its deep learning software running in the cloud.
“Moore’s Law has ebbed and flowed since its existence but only recently moved beyond doubling the density every two years. The industry has responded with heterogeneous compute using more GPUs, DSPs, FPGAs and ASICs,” said tech analyst Patrick Moorhead, referring to the array of different chips now being widely adopted to address new computing needs.
“The move to 5nm is a huge deal as something needs to go beyond 10 and 7nm because all compute, including heterogeneous compute, needs this for growth in efficiency or performance,” Moorhead said. “In other words, both are necessary to move the industry forward.”